Reading Material : Introduction to the course
Video : Course Introduction
Video : Meet Your Trainer
Reading Material : COURSE STRUCTURE GUIDE FOR STUDENTS
Reading Material: Assessment Structure
Video : Career Guidance
Reading Material : Career Opportunities After This Course
Video : Software Installation
Reading Material : Vivado Software Installation Guide
Complete Student Tour of LMS - From Login to Final Results.
Mind Map
VIDEO_01 : VLSI Frontend Design Flow Part_01
VIDEO_02 : VLSI Backend Design Flow Part_02
Summary : The Modern Miracle Chip
Reading Material : Briefing on the VLSI Design Flow
Reading Material : Project Proposal - A Structured ASIC Design Initiative
Reading Material : VLSI Design and Manufacturing Process Handbook
Reading Material : VLSI Design - A Beginner's Guide to Front-End vs. Back-End
VIDEO_01 : Explanation of Design Tools & HDL Languages
Summary : From Code to Silicon
Reading Material : A Strategic Evaluation of the Modern VLSI Front-End Design and Verification Landscape
Reading Material : Briefing Document - VLSI Design Languages and Tools
Reading Material : VLSI Hardware Description Languages and Design Tools
Reading Material : Understanding Hardware Description Languages (HDLs) - Your First Step in VLSI
VIDEO_01 : How Can We Create The Project File in Xilinx Vivado
Summary : Creating a Vivado Project
Reading Material : Xilinx Vivado Project Workflow
Reading Material : Understanding the Vivado FPGA Design Workflow
Reading Material : Xilinx Vivado Project Creation and Design Workflow
Reading Material : Xilinx Vivado Project Creation
Reading Material : Xilinx Vivado - A Professional's Guide to Project Creation
VIDEO_01 : Explanation of Logic Gates
Summary : The Secret Language
Reading Material : A Beginner's Guide to the 7 Basic Logic Gates
Reading Material : Briefing on Fundamental Digital Logic Gates
Reading Material : Onboarding Manual: Fundamentals of Digital Logic Gates
Reading Material : Study Guide for Digital Logic Gates
Mind_Map
VIDEO_01 : Types Verilog Modellings & Data Flow Modelling
VIDEO_02 : Data Flow Modelling Verilog Code Syntax
VIDEO_03 : Gate Level Modelling
VIDEO_04 : Gate Level Modelling Verilog Code Syntax
VIDEO_05 : AND Gate Implementation on FPGA
VIDEO_06 : XOR Gate Implementation on FPGA
VIDEO_07 : Behavioral Modelling
VIDEO_08 : Behavioral Modelling Verilog Code Syntax
Summary : Verilog Modelling Styles
Reading Material : The Three Fundamental Modeling Styles
Reading Material : Verilog Modeling for Logic Gates
Reading Material : Verilog Modeling Styles for Logic Gates
Reading Material : Verilog Modeling Styles Study Guide
VIDEO_01 : Implementation of Half Adder
VIDEO_02 : Implementation of Half Adder in Verilog
VIDEO_03 : Implementation of Full Adder
VIDEO_04 : Implementation of Full Adder in Verilog
VIDEO_05 : Implementation of Full Adder on FPGA
VIDEO_06 : Implementation of 4-Bit Ripple Carry Adder
Summary : Digital Adders
Reading Material : Comparative Analysis of Digital Adder Architectures in VLSI Design
Reading Material : Digital Adder Architectures
Reading Material : Digital Adders
Reading Material : Understanding Digital Adders - From Half to Full
VIDEO_01 : Behavioral If Else Condition
VIDEO_02 : Behavior If Else Condition in Verilog
VIDEO_03 : Behavioral Case Default Condition
VIDEO_04 : Behavioral Case Default Condition in Verilog
VIDEO_05 : Repeated If Else & Case Condition with Full Adder
Summary : Verilog Showdown - If vs Case
Reading Material : A Guide to if-else and case Statements
Reading Material : Making Choices in Verilog - A Clear Guide to if-else vs. case
Reading Material : Verilog Conditional Control Flow
Reading Material : Verilog Conditional Control Flow Study Guide
VIDEO_01 : Module Instantiation and it's Types & Named Instantiation
VIDEO_02 : Full Adder Using Half Adder
VIDEO_03 : Full Adder Using Half Adder in Verilog
VIDEO_04 : Implementation of Full Adder Using Half Adder on FPGA
VIDEO_05 : Named Instantiation in Verilog
VIDEO_06 : Positional Module Instantiation
VIDEO_07 : Positional Module Instantiation in Verilog
VIDEO_08 : Implementation of Ripple Carry adder on FPGA
Summary : Verilog Module Instantiation
Reading Material : A Guide to Hierarchical Digital Design
Reading Material : Hardware Design Specification - Ripple Carry Adder (RCA)
Reading Material : Module Instantiation in Verilog and SystemVerilog
Reading Material : Verilog Module Instantiation
VIDEO_01 : Implementation of Binary Multiplier
VIDEO_02 : Implementation of Binary Multiplier in Verilog
VIDEO_03 : Implementation of Binary Multiplier on FPGA
Summary : How Computers Multiply
Reading Material : A Primer on Binary Multiplier Implementation in Verilog
Reading Material : Binary Multiplier Systems - Principles and Implementation
Reading Material : Binary Multipliers
Reading Material : 2-bit and 4-bit Binary Multipliers
VIDEO_01 : Implementation of 1-Bit Comparator
VIDEO_02 : Implementation of 1-Bit Comparator in Verilog
VIDEO_03 : Implementation of 1-Bit Comparator on FPGA
Summary : How Computers Compare
Reading Material : Digital Binary Comparators
Reading Material : Digital Comparators Explained - From Single Bits to Multi-Bit Numbers
Reading Material : Study Guide for Digital Comparators
Reading Material : 1-Bit and 4-Bit Digital Comparators
Reading Material : Understanding the 4-Bit Comparator - A Step-by-Step Logic Walkthrough
VIDEO_01 : Logic Gates Using Universal Gates
VIDEO_02 : Logic Gates Using Universal Gates in Verilog
Summary : The One Gate Challenge
Reading Material : Realizing Basic Logic Gates Using Universal Gates
Reading Material : Realization of Logic Gates Using Universal NAND and NOR Gates
Reading Material : Universal Logic Gates (NAND and NOR)
Reading Material : The Magic Bricks of Digital Logic - Understanding Universal Gates
VIDEO_01 : Binary to Gray Code Conversion
VIDEO_02 : Binary to Gray Code Conversion in Verilog
VIDEO_03 : Gray to Binary Code Conversion
VIDEO_04 : Gray to Binary Code Conversion in Verilog
Summary : Binary & Grey Code
Reading Material : Binary and Gray Code Conversion
Reading Material : Synthesizable Binary and Gray Code Converters in Verilog
Reading Material : Bidirectional Binary and Gray Code Converter
Module_01 Quiz
Module_01 Assignment
Doubt Clarification Session
Video_01 : Introduction to Testbench
Video_02 : Verilog Testbench Code_01
Video_03 : Verilog Testbench Code_02
Video_04 : Verilog Testbench Code_03
Summary : Virtual Proving Ground
Reading Material : Verilog Test Bench
Reading Material : Testbench Reference Material
Reading Material : Understanding Verilog Test Benches
Reading Material : Principles of Modern Design Verification
Reading Material : Briefing Doc
Mind Map : Verilog Delays and Simulation Control
Video_01 : Verilog Delays_01
Video_02 : Verilog Delays_02
Summary : A Tale of Two Delays
Reading Material : Understanding Verilog Delays
Reading Material : Verilog Timing Control
Reading Material : Verilog Timing Control Constructs
Mind Map : Verilog Display and Monitoring System Tasks
Video_01 : Verilog Displays and Monitoring Systems_01
Video_02 : Verilog Displays and Monitoring Systems_02
Summary : Verilog Display Tasks
Reading Material : Verilog Display and Monitoring System Tasks
Reading Material : A Comparative Analysis of Verilog Display and Monitoring System Tasks
Reading Material : Verilog's Display & Monitoring Commands
Module_02 Quiz
Module_02 Assignment
VIDEO_01 : Introduction to Multiplexers & Implementation of 2-1-Mux
VIDEO_02 : Implementation of 2-1-Mux in Verilog
VIDEO_03 : Implementation of 4-1-Mux
VIDEO_04 : Implementation of 4-1-Mux in Verilog
VIDEO_05 : Implementation of 4-1-Mux on FPGA
Summary : Understanding the Multiplexer
Reading Material : Briefing on Digital Multiplexers
Reading Material : 2x1, 4x1, and 8x1 Multiplexers for Digital Systems
Reading Material : Multiplexer Study Guide
Reading Material : Understanding Multiplexers (MUX): A Beginner's Guide
VIDEO_01 : Implementation of Logic Gates Using 2-1-Multiplexer
VIDEO_02 : Implementation of Logic Gates Using Mux in Verilog_01
VIDEO_03 : Implementation of Logic Gates Using Mux in Verilog_02
VIDEO_04 : Implementation of Xor Gate Using Mux on FPGA
Summary : MUX - The Digital Shapeshifter
Reading Material : Logic Gate Realization Using 2x1 Multiplexers
Reading Material : Logic Gate Realization Using Multiplexers
Reading Material : The Multiplexer as a Digital Swiss Army Knife - How to Build Any Logic Gate
VIDEO_01 : Implementation of 4-1-Mux & 8-1-Mux Using 2-1-Mux
VIDEO_02 : Implementation of 4-1-Mux Using 2-1-Mux in Verilog
VIDEO_03 : Implementation of 4-1-Mux Using 2-1-Mux on FPGA
VIDEO_04 : Implementation of 8-1-Mux Using 2-1-Mux in Verilog
VIDEO_05 : Implementation of 3-1-Mux & 5-1-Mux Using 2-1-Mux
VIDEO_06 : Implementation of 3-1-Mux & 5-1-Mux Using 2-1-Mux in Verilog
VIDEO_07 : Implementation of 5-1-Mux Using 2-1-Mux on FPGA
Summary : Building with Digital LEGOs
Reading Material : Advanced Multiplexer Design and Implementation
Reading Material : Building Big with Small - The Magic of Hierarchical Multiplexers
Reading Material : Hierarchical and Modular Construction of Complex Multiplexers
Reading Material : Advanced Multiplexer Designs
Reading Material : Modular Multiplexing—A Hierarchical Approach to Scalable and Maintainable Digital Design
VIDEO_01 : Implementation of Adders Using Mux
VIDEO_02 : Implementation of Adders Using Mux in Verilog
VIDEO_03 : Implementation of Full Adder Using Mux on FPGA
Summary : Adder Designs - The MUX Method
Reading Material : Adder Implementation Using Multiplexers
Reading Material : Implementing High-Performance Carry-Select Adders
Reading Material : How to Build an Adder with a Switch - A Multiplexer Magic Trick
Reading Material : Adder Designs Using Multiplexers
VIDEO_01 : Implementation of Boolean Function Using Multiplexers
VIDEO_02 : Implementation of Boolean Function Using Multiplexer in Verilog
Summary : The Universal Toolkit
Reading Material : Process Guide: Implementing Boolean Functions with Multiplexers
Reading Material : Realization of Boolean Expressions Using Multiplexers
Reading Material : Study Guide: Boolean Expression Realization Using Multiplexers
Reading Material : The Magic of Multiplexers: Building Any Logic Circuit with One Component
VIDEO_01 : Introduction to De-Multiplexers & Implementation of 1-2-Demux
VIDEO_02 : Implementation of 1-2-Demultiplexer on FPGA
VIDEO_03 : Implementation of 1-4-Demultiplexer
VIDEO_04 : Implementation of 1-4 & 1-2-Demultiplexer in Verilog
Summary : The Explainer Demultiplexers
Reading Material : Demultiplexer (DEMUX) - Function, Implementation, and Application
Reading Material : Demultiplexer (DEMUX) Study Guide
Reading Material : Realizing Logic Gates with Demultiplexers
Reading Material : 1x2 and 1x8 Demultiplexer (DEMUX) Circuits in Verilog
Reading_material : Understanding the Demultiplexer (DEMUX)
VIDEO_01 : Implementation of 1-4 & 1-8-Demux Using 1-2-Demux
VIDEO_02 : Implementation 1-4 & 1-8-Demux Using 1-2-Demux in Verilog
VIDEO_03 : Implementation 1-4 Using 1-2-Demux on FPGA
Summary : Building Big with Small Blocks
Reading Material : Understanding Hierarchical Design in Digital Circuits
Reading Material : Adopting a Modular, Hierarchical Methodology for Digital Circuit Design
Reading Material : Hierarchical Implementation of a 1:4 Demultiplexer
Reading Material : Hierarchical Demultiplexer Design
Reading Material : Hierarchical 1:4 Demultiplexer Module
VIDEO_01 : Implementation of Logic Gates Using Demux
VIDEO_02 : Implementation of Logic Gates Using Demux in Verilog
VIDEO_02 : Implementation of Nand gate Using Demux On FPGA
Summary : Building Logic with DEMUX
Reading Material : Implementation of Logic Gates Using Demultiplexers
Reading Material : Implementing Logic Gates with Demultiplexers
Reading Material : Realization of Basic Logic Gates Using a 1:2 Demultiplexer
Reading Material : How a Simple Demultiplexer Can Build Logic Gates
Module_03 Quiz
Module_03 Assignment
Video_01 : Introduction to Decoders & Implementation 1-to-2 Decoder
Video_02 : Implementation of 2-to-4 & 3-to-5 Decoders
Video_03 : Implementation 1-to-2 Decoder in Verilog
Video_04 : Implementation of 2-to-4 & 3-to-5 Decoders in Verilog
Video_05 : Implementation of 2-to-4 Decoder on FPGA
Summary : The Digital Locksmith
Reading Material : Briefing on Digital Decoders - Principles and Implementation
Reading Material : Decoders and Encoders
Reading Material : A Family of N-to-2ⁿ Binary Decoders
Reading Material : Understanding Digital Decoders
Video_01 : Implementation of Half Adder & Full Adder Using Decoder
Video_02 : Implementation of Half Adder Using Decoder in Verilog
Video_03 : Implementation Full Adder Using 3-to-8 Decoder in Verilog
Video_04 : Implementation Half Adder Using 2-to-4 Decoder on FPGA
Summary : Adders with Decoders
Reading Material : Building Digital Adders with Decoders - A Beginner's Guide
Reading Material : Implementation of Digital Adders Using Decoders
Reading Material : Implementing Adders with Decoders
Reading Material : Full and Half Adder Implementation using Decoders
Video_01 : Implementation of 3-to-8 Decoder Using 2-to-4 Decoder
Video_02 : Implementation of 4-to-16 Decoder Using 2-to-4 Decoder_01
Video_03 : Implementation of 4-to-16 Decoder Using 2-to-4 Decoder_02
Video_04 : Implementation of 3-to-8 Decoder Using 2-to-4 Decoder in Verilog
Video_05 : Implementation of 4-to-16 Decoder Using 2-to-4 Decoder in Verilog
Video_06 : Implementation of 3-to-8 Decoder Using 2-to-4 Decoder on FPGA
Summary : Building Big From Small
Reading Material : Briefing on Hierarchical Decoder Design Principles
Reading Material : Building Big Circuits from Small Pieces - The Magic of Hierarchical Decoders
Reading Material : Decoder Design Study Guide
Reading Material : Design Specification - Hierarchical Decoders in Verilog
Video_01 : Implementation of 2-to-4 Decoder and 2 1 Encoder Using 1-to-2 Mux
Video_02 : Implementation of 2-to-4 Decoder Using 2-to-1 Mux and 1-to-2 Demux in Verilog
Video_03 : Implementation of 2-to-4 Decoder Using 2-to-1 Mux on FPGA
Summary : Digital LEGOs
Reading Material : Implementation of Decoders and Demultiplexers
Reading Material : Building a Decoder from Multiplexers - A Step-by-Step Guide
Reading Material : Decoder and Demultiplexer Circuits
Reading Material : Alternative Implementations of Decoder and Demultiplexer Circuits
Video_01 : Introduction to Encoders
Video_02 : Implementation of 4-to-2 Encoder Verilog Code
Video_03 : Implementation of 4-to-2 Encoder on FPGA
Video_04 : 8-to-3 Encoder
Video_05 : Implementation of 8-to-3 Encoder Verilog Code
Summary : Encoders - The Digital Shorthand
Reading Material : Briefing on Digital Logic Encoders
Reading Material : Introduction to Encoders
Reading Material : Standard Encoder Logic Circuits
Reading Material : Understanding Digital Encoders
Video_01 : Introduction to Priority Encoder
Video_02 : Implementation of 4-to-2 Priority Encoder Verilog Code
Summary : Explainer - Priority Encoder
Reading Material : The Priority Encoder
Reading Material : Priority Encoder Study Guide
Reading Material : 4x2 Priority Encoder
Reading Material : Understanding the Priority Encoder
Module_04 quiz
Module_04 Assignment
Video_01: Event Stratified Queue
Video_02: Non Blocking Assignment Event Regions (NBA)
Summary : Demystifying Verilog Queue
Reading Material : Briefing on Verilog Event Stratified Queries
Reading Materials : A Journey Through a Verilog Simulation Time Slot
Reading Material : RTL Design Best Practices
Reading Material : Standardization of Verilog Coding Practices for Predictable Simulation
Quiz : Event Stratified Queries & Verilog Event Queue
Assignment
Video : RTL Coding Guidelines
Summary : Verilog Blocking Vs Non Blocking
Reading Material : A Beginner's Guide to Verilog Simulation: Step-by-Step Examples
Reading Material : An Analysis of Verilog Event Scheduling and Simulation Nuances
Reading Material : Briefing on Verilog RTL Coding Guidelines and Simulation Semantics
Reading Material : The Golden Rules of Verilog Assignments: A Beginner's Guide
Quiz : RTL Coding Guidelines and Verilog Simulation
Video : Verilog Blocking Assignments
Reading Material : Demystifying Verilog Assignments: A Beginner's Guide to = vs. <=
Reading Material : Technical Memorandum: Verilog Assignment Operators
Reading Material : Understanding Verilog's Power: Blocking (=) vs. Non-Blocking (<=) Assignments
Reading Material : Verilog Assignment Mechanisms: A Comparative Briefing
Reading Material : Best Practices for Blocking and Non-Blocking Assignments
Quiz - Verilog Assignments
Video : Incomplete Sensitivity List
Summary : The Hidden Code Bug
Reading Material : Briefing on Verilog Design Pitfalls: The Incomplete Sensitivity List
Reading Material : Ensuring Correctness with Complete Verilog Sensitivity Lists
Reading Material : Code Walkthrough: Understanding an Incomplete Sensitivity List in Verilog
Reading Material : The Critical Importance of Complete Verilog Sensitivity Lists
Reading Material : Understanding the Verilog always Block Sensitivity List
Quiz - Incomplete Sensitivity List
Video : Nested If Else
Video : Nested If Else in Verilog
Summary : The Hidden Flaw
Reading Material : Briefing on Latch Inference in RTL Design
Reading Material : From Code to Circuit: How a Missing 'Else' Creates Unwanted Hardware
Reading Material : Mandating Comprehensive else Conditions for Multiplexer Inference
Reading Material : Avoiding Unintentional Latches in RTL Design
Reading Material : The Hidden Trap: How Incomplete Logic Creates Unintentional Latches
Quiz :
Video : Use of Case Constructs in Verilog
Reading Material : Briefing on Verilog Case Construct Usage
Reading Material : Mitigating Unintentional Latch Inference in Verilog case Constructs
Reading Material : Understanding Unintentional Latches in Verilog Case Statements
Reading Material : Understanding Verilog Case Constructs: A Beginner's Guide
Quiz
Module Assignment
Module 5 Quiz
Video : Sequential Circuits
Summary : The Circuit That Remembers
Reading Material : Sequential Circuits
Reading Material : The Architecture and Principles of Sequential Circuits
Reading Material : The Core Idea of Sequential Circuits
Reading Material : The Power of Memory
Video_01 : Introduction to Latches and Flip Flops
Video_02 : Implementation of SR Latch Using NAND Verilog Code
Summary : The Simplest Memory
Reading Material : Understanding Digital Latches
Reading Material : SR and D Digital Latches
Reading Material : An Introduction to Digital Latches
Video_01 : Introduction to Flip-Flops
Video_02 : Implementation of SR Flip-Flop Verilog Code
Summary : The Flip-Flop Explained
Reading Material : Analysis of Flip-Flop Fundamentals and the SR Flip-Flop
Reading Material : The Role of Flip-Flops in Digital Logic Design
Reading Material : The Building Blocks of Digital Memory
Reading Material : Introduction to Flip-Flops
Video_01 : D Flip-Flop
Video_02 : D Flip Flop Verilog Code
Summary : Digital Memory Heartbeat
Reading Material : Briefing on the D Flip-Flop
Reading Material : Understanding the D Flip-Flop
Reading Material : D Flip-Flop
Video_01 : JK Flip-Flop
Video_02 : JK Flip-Flop Verilog Code
Summary : JK Flip-Flop The Superpower
Reading Material : JK Flip-Flop Briefing
Reading Material : JK Flip-Flop Technical Overview
Reading Material : Introduction to JK Flip-Flop
Reading Material : JK Flip-Flop
Video_01 : T Flip-Flop
Video_02 : Implementation of T Flip-Flop
Summary : The T-Flip Flop
Reading Material : T Flip-Flop
Reading Material : T-Type Flip-Flop
Reading Material : Understanding the T Flip-Flop
Video_01 : SR Flip-Flop Using JK Flip-Flop
Video_02 : Implementation of SR Flip-Flop Using JK Flip-Flop
Summary : SR from JK Flip-Flop
Reading Material : Implementing an SR Flip-Flop with a JK Flip-Flop
Reading Material : Understanding SR and JK Flip-Flops
Reading Material : SR Flip-Flop Implementation Using a JK Flip-Flop
Video_01 : SR Flip-Flop Using D Flip_Flop
Video_ 02 : Implementation of SR Flip-Flop Using D Flip-Flop
Summary : SR from D Flip-Flop
Reading Material : Implementation of an SR Flip-Flop Using a D Flip-Flop
Reading Material : D Flip-Flop Act Like an SR Flip-Flop
Reading Material : SR Flip-Flop Implementation Using D Flip-Flop
Video : Master Slave Flip-Flop
Summary : The Digital Air Lock
Module_06 Quiz
Module_06 Assignment
Video_01 : Introduction to Counters
Video_02 : Implementation of Up & Down Counters
Summary : Explainer Digital Counters
Reading Material : An Analysis of Digital Counters
Reading Material : Digital Counter Technology
Reading Material : Understanding Digital Counters
Reading Material : Foundational Principles of Sequential Counter Circuits
Video_01 : Introduction to Asynchronous Counters
Video_02 : Asynchronous Counters Verilog Code
Video_03 : Asynchronous Counter Using T Flip-Flop
Video_04 : Verilog Code for 2-bit Asynchronous Counter
Summary : Asynchronous Counters
Reading Material : Briefing on Asynchronous Counters
Reading Material : A Technical Analysis of Asynchronous (Ripple) Counters
Reading Material : Understanding Asynchronous (Ripple) Counters
Reading Material : 2-Bit Asynchronous Up-Counter
Video_01 : Synchronous Counters
Video_02 : Implementation of Synchronous Counters_01
Video_03 : Implementation of Synchronous Counters_02
Video_04 : 3-bit Synchronous Counters Using T Flip-Flop
Summary : Synchronous Counters
Reading Material : Briefing on Synchronous Counters
Reading Material : Synchronous Counter Design and Principles
Reading Material : Understanding Synchronous Counters
Video_01 : Introduction to Mod-N Counters
Video_02 : Design Steps for Mod-N Counters
Video_03 : Decade Counter
Summary : Understanding Mode-N Counters
Reading Material : Briefing on Mod-N Counters
Reading Material : Mod-N Counter Design and Implementation
Reading Material : Understanding Mod-N Counters
Reading Material : Mod-N Counters
VIDEO_01 : Implementation of Ring Counter
VIDEO_02 : Implementation of Ring Counter in Verilog
VIDEO_03 : Implementation of Twisted Ring Counter
VIDEO_04 : Implementation of Twisted Ring Counter in Verilog
Summary : Ring vs Johnson Counters
Reading Material : Analysis of Ring and Twisted Ring Counters
Reading Material : Understanding Ring and Twisted Ring Counters
Reading Material : Ring Counter and Twisted Ring Counter
Reading Material : Comparing the Ring and Twisted Ring (Johnson) Designs
VIDEO_01 : Parameterized n-bit Counters_01
VIDEO_02 : Parameterized n-bit Counters_02
Summary : Parameterized Verilog Modules
Reading Material : Scalable Hardware Design with Verilog Parameters and Generate Statements
Reading Material : Unlocking Flexibility in Verilog - A Guide to Parameterized Modules
Reading Material : Digital Systems Study Guide - Parameterized Verilog Modules
Reading Material : Briefing on Parameterized Verilog Modules
VIDEO_01 : Frequency Division of Clock
VIDEO_02 : Frequency Division of Clock in Verilog
Summary : Frequency Division Counters
Reading Material : Implementing Asynchronous Ripple Counters for Frequency Division
Reading Material : Understanding Frequency Division with Flip-Flops
Reading Material : Frequency Division Counters
Reading Material : Study Guide for Frequency Division Counters
VIDEO_1 : Implementation of Digital Clock
VIDEO_2 : Implementation of Digital Clock in Verilog
VIDEO_3 : Interview Questions & Answers
Module_07 Quiz
Module_07 Assignment
Video: Introduction to Shift Register & SISO
Video : Verilog Code of SISO Register
Summary : Shift Registers & SISO
Reading Material : Shift Register Algorithms and Implementation
Reading Material : A Beginner's Guide for Shift Registers
Reading Material : Implementation and Testing Guide of Verilog SISO Shift Register
Reading Material : Technical Overview of Shift Register Architectures and Algorithms
Introduction to Shift Register & SISO
Video_01 : Introduction to SIPO
Video_02 : Verilog Code of SIPO Register
Reading Material : SIPO Shift Register
Reading Material : SIPO Shift Register: An Analysis
Reading Material : 4-Bit SIPO Shift Register
SIPO Quiz
Video : PIPO Register
Summary : PIPO
Reading Material : PIPO Shift Register
Reading Material : A Design Walkthrough
Reading Material : 4-Bit PIPO Shift Register Technical Specification
Understanding the Parallel-In Parallel-Out (PIPO) Shift Register: A Beginner's Guide
PIPO Quiz
Summary : PISO Register
Reading Material : Understanding the PISO Shift Register
Reading Material : Analysis of the PISO Shift Register
Design Document: 4-Bit Parallel-In, Serial-Out (PISO) Shift Register
Technical Specification: 4-Bit Parallel-In Serial-Out (PISO) Shift Register
PISO Quiz
Module 8 - Quiz
Module_08 Assignment
VIDEO_01 : Introduction to FSM's
VIDEO_02 : Component's of Finite State Machine's
Summary : Secret Brain of Everyday Tech
Reading_Material : A Beginner's Guide to Finite State Machines
Reading_Material : Briefing on Finite State Machines (FSMs)
Reading_Material : Design Specification: Finite State Machine (FSM) Implementation
Reading_Material : Finite State Machines Study Guide
VIDEO_01 : Mealy Machine
VIDEO_02 : Moore FSM
Summary : Melay vs Moore FSM
Reading_Material : Mealy vs. Moore Models
Reading_Material : Design Specification: Finite State Machine (FSM) Control System Architecture
Reading_Material : Finite State Machines (FSMs) Study Guide
Reading_Material : Mealy vs. Moore: Understanding the Two Flavors of State Machines
VIDEO_01 : Mealy_Overlapping_101_Sequence_Detector
VIDEO_02 : Mealy_Overlapping_101_Sequence_Detector _Verilog Code_Implementation
VIDEO_03 : Mealy_Overlapping_101_Sequence_Detector_Final_Circuit.
VIDEO_04 : Mealy_Overlapping_1010_Sequence_Detector
VIDEO_05 : Mealy_Overlapping_1010_Sequence_Detector_Final_Circuit
VIDEO_06 : Mealy_Overlapping_1010_Sequence_Detector_Verilog_code
Summary : The Digital Secret Knock
Reading_Material : Mealy Finite State Machines for Overlapping Sequence Detection
Reading_Material : Mealy FSM Design Specification: Overlapping Sequence Detectors for "1010" and "101"
Reading_Material : Study Guide: Mealy Finite State Machines for Overlapping Sequence Detection
Reading_Material : Understanding Mealy Machines: A Beginner's Guide to Detecting a "1010" Sequence
VIDEO_01 : Mealy Non Overlapping 101 Sequence Detector
VIDEO_02 : Mealy Non Overlapping 101 Sequence Detector Verilog Code Implementation
VIDEO_03 : Mealy Non Overlapping 1010 Sequence Detector
VIDEO_04 : Mealy Non Overlapping 1010 Sequence Detector Verilog Code
Summary : The Digital Detective
Reading_Material : Briefing on Mealy Non-Overlapping Sequence Detectors
Reading_Material : Design Specification: Mealy Non-Overlapping Sequence Detectors
Reading_Material : Study Guide: Mealy Non-Overlapping Sequence Detectors
Reading_Material : Understanding Your First Sequence Detector: A Mealy Machine for "101"
VIDEO_01 : Moore Overlapping 101 Sequence Detector
VIDEO_02 : Moore Overlapping 101 Sequence Detector Verilog Code
VIDEO_03 : Moore Overlapping 1010 Sequence Detector
VIDEO_04 : Moore Overlapping 1010 Sequence Detector Verilog Code
Reading_Material : An Introduction to Moore Finite State Machines
Reading_Material : Moore FSM for Overlapping Sequence Detection
Reading_Material : Moore FSM Overlapping Sequence Detector: Design Specification
Reading_Material : Moore FSM Overlapping Sequence Detectors Study Guide
VIDEO_01 : Moore Non Overlapping 101 Sequence Detector
VIDEO_02 : Moore Non Overlapping 101 Sequence Detector Verilog Code
VIDEO_03 : Moore Non Overlapping 1010 Sequence Detector
VIDEO_04 : Moore Non Overlapping 1010 Sequence Detector Verilog Code
Reading_Material : Moore FSM Design Specification: Non-Overlapping Sequence Detectors
Reading_Material : Moore FSM for Non-Overlapping Sequence Detection
Reading_Material : Study Guide: Moore FSM Non-Overlapping Sequence Detectors
VIDEO_01 : Interview Questions Part 1
VIDEO_02 : Interview Questions Part 2
Summary : Brains of Simple Machine
Reading_Material : A Beginner's Guide to Finite State Machines (FSMs)
Reading_Material : Finite State Machine Design Principles and Applications
Reading_Material : Solving Problems with Finite State Machines: A Practical Walkthrough
Module_09 Quiz
Module_09 Assignment
VIDEO_01 : Introduction_to_the_EDGE_Artix-7_FPGA_Board
Reading_Material : EDGE Artix-7 FPGA Board: Technical Specification
Reading_Material : EDGE Artix-7 FPGA Development Board – Technical Briefing
Reading_Material : EDGE Artix-7 FPGA Development Board – Study Guide
Reading_Material : Introduction: Welcome to the World of Digital Design
VIDEO_01 : Frequncy_Division_With_Examples_LEDS
VIDEO_02 : Frequncy_Division_With_JKFF_Implementation
VIDEO_03 : Frequncy_Division_With_JKFF_Implementation_on_Xilinx_Vivado
VIDEO_04 : Frequncy_Division_With_JKFF_Implementation_on_FPGA
VIDEO_05 : Frequncy_Division_With_Counter_Implementation_on_Xilinx_Vivado
VIDEO_06 : Frequncy_Division_With_Counter_Implementation_on_FPGA
Reading_Material : Briefing on Sequential Circuit Implementation and Observation on the EDGE Artix-7 FPGA Board
Reading_Material : Study Guide: Frequency Division on the EDGE Artix-7 FPGA Board in Sequential Circuits
Reading_Material : The Pedagogical Imperative of Frequency Division in FPGA-Based Digital Logic Education on the EDGE Artix-7 FPGA Board
Reading_Material : Why Digital Circuits on the EDGE Artix-7 Need a “Slow-Motion Button”: Understanding Clock Speed
VIDEO_01 : Introduction_to_the_4_Seven_Segement
VIDEO_02 : Numerical_Printing_Implementation
VIDEO_03 : Numerical_Printing_Implementation_on_Xilinx_Vivado
VIDEO_04 : Numerical_Printing_Implementation_on_FPGA
VIDEO_05 : Counter_Implementation_on_Xilinx_Vivado
VIDEO_06 : Counter_Implementation_on_FPGA
Reading_Material : EDGE Artix-7 FPGA Board: Four-Digit Seven-Segment Display Technical Specification
Reading_Material : Study Guide: The EDGE Artix-7 Seven-Segment Display
Reading Material : The EDGE Artix-7 Seven-Segment Display: Operational Overview
Reading_Material : EDGE Artix-7 Seven-Segment Display
VIDEO_01 : Introduction_to_LCD_PART_01
VIDEO_02 : Introduction_to_LCD_PART_02
VIDEO_03 : Implementation_of_LCD_on_Xilinx_Vivado
VIDEO_04 : Implementation_of_LCD_on_Xilinx_Vivado
Reading_Material : Application : Integrating the 16x2 LCD with the EDGE Artix-7 FPGA Board and Spartan 3E FPGA Board
Reading_Material : Briefing Document: FPGA-Interfaced 16x2 LCD (EDGE Artix-7 + Spartan-3E Comparison)
Reading_Material : IP Core Technical Specification: HD44780 4-Bit LCD Controller
Reading_Material : LCD Peripheral Study Guide
VIDEO_01 : Introduction_to_VGA
VIDEO_02 : Implementation of VGA on Xilinx Vivado
VIDEO_03 : Implementation of VGA on FPGA
Reading_Material : VGA (Video Graphics Array) Technology Briefing
Reading_Material : How VGA Works: Painting Pictures with Signals
Reading_Material : Technical Specification: 640x480 VGA Controller for FPGA Implementation
Reading_Material : VGA (Video Graphics Array) Study Guide
Video : Capstone Project Part - 01
Video : Capstone Project Part - 02
Video : How to Write a Research Paper
IJERT Paper Template
ICTACT Paper Template
Submit you project report
PROJECT 1 | TRAFFIC_LIGHT_CONTROLLER
Report: TRAFFIC_LIGHT_CONTROLLER
Presentation : TRAFFIC_LIGHT_CONTROLLER
PROJECT 2 | VGA_NO_SIGNAL
Report - VGA No Signal
Presentation: VGA No Signal
PROJECT 3 | SPI_ACCELEROMETER
Report : SPI_ACCELEROMETER
Presentation : SPI_ACCELEROMETER
PROJECT 4 | VGA_DIGITAL_CLOCK
Report : VGA_DIGITAL_CLOCK
Presentation : VGA_DIGITAL_CLOCK
PROJECT 5 | DIGITAL CLOCK
Report : DIGITAL_CLOCK
Presentation : DIGITAL_CLOCK
PROJECT 6 | KEYBOARD_INTERFACING_WITH_FPGA
Report : KEYBOARD_INTERFACING_WITH_FPGA
Presentation : KEYBOADR_INTERFACING_WITH_FPGA
PROJECT 7 | GCD
Report : GCD
Presentation : GCD
PROJECT 8 | ELEVATOR
Report : ELEVATOR
Presentation : ELEVATOR
PROJECT 9 | VGA_OBJECT_ANIMATION & COLLISION_DETECTION
Report : VGA_OBJECT_ANIMATION & COLLISION_DETECTION
Presentation : VGA_OBJECT_ANIMATION & COLLISION_DETECTION
PROJECT 10 | VGA_PONG_GAME
Report : VGA_PONG_GAME
Presentation : VGA_PONG_GAME
PROJECT 11 | STOP WATCH
Report : STOP_WATCH
Presentation : STOP_WATCH
PROJECT 12 | FIFO_MEMORY
Report : FIFO_MEMORY
Presentation : FIFO_MEMORY
PROJECT 13 | I2C PROTOCOL
Report : I2C_PROTOCOL
Presentation : I2C_PROTOCOL
PROJECT 14 | VOTING MACHINE
Report : VOTING_MACHINE
Presentation : VOTING_MACHINE
PROJECT 15 | VENDING_MACHINE
Report : VENDING_MACHINE
Presentation : VENDING_MACHINE
PROJECT 16 | CAR_PARKING_SYSTEM
Report : CAR_PARKING_SYSTEM
Presentation : CAR_PARKING_SYSTEM
Report : FSM_CONTROLLED_CALCULATOR
Presentation : FSM_CONTROLLED_CALCULATOR
Report : UART_RECIEVER
Presentation : UART_RECIEVER
Report : CANDY_MACHINE
Presentation : CANDY_MACHINE
Report : VGA_DIGITAL_CALENDER
Presentation : VGA_DIGITAL_CALENDER